The present invention relates to a voltage converter which lowers an external supply voltage within a semiconductor integrated circuit chip to drive circuits on the chip having small geometries.
Reduction in the geometries of devices such as bipolar or MOS transistors has been accompanied by a lowering in the breakdown voltages of the devices, which has made it necessary to lower the operating voltage of small geometry devices with an integrated circuit. From the viewpoint of users, however, a single voltage source of for example 5 V which is easy to use is desirable. As an expedient for meeting such different requests of IC manufacturers and the users, it is considered to be necessary to lower the external supply voltage V.sub.CC within a chip and to operate the small geometry devices with the lowered voltage V.sub.L.
FIG. 1 shows an example of such an expedient, in which the circuit A' of the whole chip 10 including, e.g., an input/output interface circuit is operated with the internal supply voltage V.sub.L lowered by a voltage converter 13.
FIG. 2 shows an integrated circuit disclosed in Japanese Patent Application No. 56-57143 (Japanese Laid-open Patent Application No. 57-172761). The small geometry devices are employed for a circuit A determining the substantial density of integration of the chip 10, and are operated with the voltage V.sub.L obtained by lowering the external supply voltage V.sub.CC by means of a voltage converter 13. On the other hand, devices of comparatively large geometries are employed for a driver circuit B including, e.g., an input/output interface which does not greatly contribute to the density of integration which are operated by applying V.sub.CC thereto. Thus, a large-scale integrated circuit (hereinbelow, termed "LSI") which operates with V.sub.CC when viewed from outside the chip becomes possible.
However, when such an integrated circuit is furnished with the voltage converter, an inconvenience is involved in an aging test which is performed after the final fabrication step of the integrated circuit.
The terminology "aging test" as used herein identifies a test performed after the final fabrication step of the integrated circuit during which voltages higher than in an ordinary operation are intentionally applied to the respective transistors in the circuit to test the integrated circuit for break down due to an inferior gate oxide film.
The aforementioned voltage converter in Japanese Patent Application No. 56-57143 functions to feed the predetermined voltage. Therefore, the circuit fed with the supply voltage by the voltage converter cannot be subjected to the aging test.
In order to solve this problem, an invention disclosed in U.S. Pat. No. 4,482,985 has previously been made, but it has had difficulty in the performance for actual integrated circuits. As illustrated in FIGS. 2 to 6 in that patent, according to the cited invention, an internal voltage increases up to an aging point rectilinearly or with one step of change as an external supply voltage increases. Accordingly, the internal voltage changes greatly with the change of the external supply voltage. This has led to the disadvantage that the breakdown voltage margins of small geometry devices in an ordinary operation become small.